In the integrated circuit field, scan testing involves introducing sequences of ones and zeros, called scan bits, into the integrated circuits for testing them. Scan compression is a way of reducing the volume of such bits sent from the tester to an integrated circuit.
Scan compression is mainstream technology today. A Glossary is provided in TABLE 1.
For some other background, see U.S. Pat. Nos. 7,657,790 and 7,743,302, and U.S. Published Patent Applications 20090228749 and 20050060625.
Hitherto, scan compression architectures have had three components:    1. Decompressor: Decompresses input channel data into internal scan-ins. (A respective scan channel pertains to any given set of scan chains among a number of such sets that make up all the scan chains in the integrated circuit.) Different decompressor architectures are available in the industry, e.g. XOR decompressor, mux/demux decompressor, LFSR (Linear Feedback Shift Register) based decompressor.    2. Compactor/Compressor: Compresses internal scan-outs data into output channels. Different compressor architectures are available in the industry for e.g. XOR compressor, and MISR (Multiple Input Signature Register) based compressor. These conventional compressors are susceptible to unknowns (Xs) in the circuit. For example, an unknown X in one internal STUMP can corrupt a whole signature in an MISR based compressor. An unknown X can cause masking of multiple internal scan chains (STUMPS) in an Xor (exclusive-OR) based compressor. So the presence of Xs can cause substantial test coverage loss.    3. X-tolerance Logic: X-tolerance is a DFT technique to provide immunity to compressor from unknowns (Xs) in the functional circuit under test (DUT). Logic is provided to block the internal scan chain having such unknowns (Xs), such as by including an AND gate per internal scan chain. A second part is control logic that generates blocking controls for the AND gates. Control logic programmation can be done through ATPG (if control logic is getting input data from decompressor or from top level input channels) or through external interface like IEEE 1500 scan interface of FIG. 8, etc.
X-tolerance techniques that overcome current industry architecture limitations and provide better compression and debug capabilities are needed and would be most desirable. For instance, suppose an architecture always bypasses the compactor if one or more chains are having Xs, to prevent merging of multiple scan chains in the compactor, and hence prevent corruption of the compacted result by Xs. However, this results in significant loss of compression since the compactor is bypassed in presence of Xs.
Compressed scan chains hitherto have been difficult to use to do debug and result in generation of bypass patterns to isolate the flip-flop that is failing. In some cases a tool can generate patterns where internal scan chains are observed but this means regeneration of patterns and does neither mean that the same data will be observed, nor guarantee same paths will be excited, and has other problems.
While test data compression is useful to reduce test data volume and test application time, the reduced observability (due to output response compaction) results in two new issues:
(a) Tasks of debug and diagnostics, wherein the cause of one or more failing outputs in one or more cycles must be diagnosed to one or a set of flip-flops in the design (which in turn drive these outputs), are rendered more difficult. Difficulty arises since (i) the fault localization to the set of failing flip-flops must now be performed with less volume of output data, i.e. reduced observability, and (ii) a given fault may be exercised fewer times as the input decompressor drives few primary scan inputs into a larger number of internal scan inputs, thereby impairing the ability to excite a fault multiple times.
(b) Distinguishing groups of internal scan chains for the purpose of test coverage improvement is rendered more difficult since per cycle individual scan chain observability is no longer possible, on account of multiple internal scan chain outputs being grouped together into fewer primary scan outputs through the output compactor logic.
The issues in (a) and (b) are addressed traditionally by switching the circuit operation from scan compression mode to a prior type of a scan bypass mode. The latter has inherent disadvantages of (i) requiring a larger number of test cycles and (ii) of introducing a different state of the circuit as compared to that which actually caused a pattern to fail.
In view of the above problems, it would be desirable to somehow provide solutions in this field that can address the problems and be economical in terms of chip real estate, test time and test complexity.